 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE ClockWorksTM SY10E111 SY100E111 FEATURES s s s s s s s Low skew Extended 100E VEE range of -4.2V to -5.5V Guaranteed skew limits Differential design VBB output Enable input Fully compatible with industry standard 10KH, 100K I/O levels s 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E111 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distribution in new, highperformance ECL systems. They accept one differential or single-ended input, with VBB used for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the E111 shares a common set of "basic" processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay. To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. ln most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO as the pair(s) being used on that side) in order to maintain minimum skew. The VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only. When using VBB for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01F capacitor. BLOCK DIAGRAM Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 IN IN EN Q5 Q6 Q6 Q7 Q7 Q8 VBB Q8 Q4 Q4 Q5 Rev.: B Amendment: /2 1 Issue Date: February, 1998 Micrel ClockWorksTM SY10E111 SY100E111 PIN CONFIGURATION Q1 VCCO Q2 PIN NAMES Pin Function Differential Input Pair Enable Input Differential Outputs VBB Output VCC to Output Q0 Q0 Q1 Q2 IN, IN EN 25 24 23 22 21 20 19 VEE EN IN VCC IN VBB NC 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 Q3 Q3 Q4 VCCO Q4 Q5 Q5 Q0, Q0 -- Q8, Q8 VBB VCCO PLCC TOP VIEW J28-1 16 15 14 13 12 Q8 Q8 Q7 VCCO Q7 DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol VBB Parameter Output Reference Voltage Input HIGH Current Power Supply Current 10E 100E 10E 100E Min. -1.38 -1.38 -- -- -- Typ. -- -- -- 48 48 Max. TA = +25C Min. Typ. -- -- -- 48 48 Max. TA = +85C Min. Typ. -- -- -- 48 55 Max. -1.19 -1.26 150 60 69 A mA 60 60 -- -- 60 60 -- -- -- -- Unit V -1.27 -1.35 -1.26 -1.38 150 -- -1.25 -1.31 -1.26 -1.38 150 -- Condition -- IIH IEE TIMING DIAGRAMS IN IN ts EN 50% EN Q Q 75 mV Figure 1. Set-up Time Figure 2. Hold Time Q6 Q6 IN IN th 50% 75 mV Q Q 75 mV 75 mV IN IN tr EN 50% Q Q Figure 3. Release Time 2 Micrel ClockWorksTM SY10E111 SY100E111 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output IN (differential) IN (single-ended) Enable Disable Within-Device Skew Set-up Time, EN to IN Hold Time, IN to EN Release Time, EN to IN Minimum Input Swing Common Mode Range Rise/Fall Times 20% to 80% TA = +25C TA = +85C Max. 630 730 850 850 50 -- -- -- -- -0.4 600 ps ps ps ps mV V ps Unit ps 430 330 450 450 -- 200 0 300 250 -1.6 275 -- -- -- -- 25 0 -200 100 -- -- 375 630 730 850 850 50 -- -- -- -- -0.4 600 430 330 450 450 -- 200 0 300 250 -1.6 275 -- -- -- -- 25 0 -200 100 -- -- 375 630 730 850 850 50 -- -- -- -- -0.4 600 430 330 450 450 -- 200 0 300 250 -1.6 275 -- -- -- -- 25 0 -200 100 -- -- 375 1 2 3 3 4 5 6 7 8 9 -- Condition(1-9) Min. Typ. Max. Min. Typ. Max. Min. Typ. tSKEW tS tH tR VPP VCMR tr tf NOTES: 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 3. Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition on Q (or a negative transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the 50% point of a negative transition on Q (or a positive transition on Q). 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 5. The set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than 75mV to that IN/IN transition (see Figure 1). 6. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response greater than 75mV to that IN/IN transition (see Figure 2). 7. The release time is the minimum time that EN must be de-asserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and output transition times (see Figure 3). 8. VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP (min.) is AC limited for the E111, as a differential input as low as 50mV will still produce full ECL levels at the output. 9. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). PRODUCT ORDERING CODE Ordering Code SY10E111JC SY10E111JCTR SY100E111JC SY100E111JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 3 Micrel ClockWorksTM SY10E111 SY100E111 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
Price & Availability of SY10E111
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |